Recently, as one of 3-dimensional resistance-change memory cell arrays, a cell array structure that can avoid degradation in the film quality in the manufacturing process and reduce the manufacturing cost is proposed (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2008-181978 and 2009, Symposium on VLSI Technology Digest of Technical Papers, pp. 26-27). With the above cell array structure, a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure. Then, resistance-change films are sandwiched between the horizontal electrodes and the vertical electrodes to configure a cell array structure.
However, with this type of cell array structure, the following problem occurs. That is, with the resistance-change memory cell array, there occurs a case where it is desired to preferentially reduce a leakage current that flows in an unselected cell and a case where it is desired to preferentially supply a sufficiently large current to a selected cell according to the scale and application of the array. However, it is difficult to optimize the above requirements according to the characteristics required for the array. Specifically, in the large-scale array, a leakage current flowing in an unselected cell at the data read time or data write/erase time cannot be neglected, and therefore, there occurs a problem that the power consumption becomes larger as the integration density is more enhanced. Further, in the array that is required to have a high-speed response characteristic, there occurs a problem that a switching yield is lowered if a sufficiently large current cannot be supplied to a selected cell.